1. Technical Field
The present invention relates to integrated circuits in general, and in particular to filter circuits. Still more particularly, the present invention relates to a circuit for filtering single event effect induced glitches.
2. Description of the Prior Art
In digital systems, signals on a signal line are transmitted at two voltage levels, namely, a logical xe2x80x9c0xe2x80x9d (low voltage level) and a logical xe2x80x9c1xe2x80x9d (high voltage level). A transition from a logical xe2x80x9c0xe2x80x9d to a logical xe2x80x9c1xe2x80x9d and then back to a logical xe2x80x9c0xe2x80x9d on a signal line signifies a pulse on the signal line. The duration in time between the two transitions is commonly referred to as a pulse width. Sometimes, noise and/or unsynchronized circuit operations, typically known as glitches, may cause unexpected transitions on the signal line. A glitch, as used herein, is defined as any pulse present on a signal line having a pulse width less than a pre-determined pulse width. For example, if a digital system designed to have a signal line carries signals with pulses of at least n nanoseconds in width, any pulse having a width of less than n nanoseconds may be considered a glitch. Furthermore, a glitch may correspond to a high or low voltage spike or to an unexpected transition from the current voltage level to the opposite level and back again. to an unexpected transition from the current voltage level to the opposite level and back again.
In addition to noise and/or unsynchronized circuit operations, a single event effect (SEE) can also cause glitches. An SEE is the result of an ion transitioning through a semiconductor structure and depositing charges on a critical circuit node within that semiconductor structure. Generally, SEE can occur when a cosmic particle strikes a combinational logic node, and a voltage glitch of about 100 ps to 300 ps may be generated at the combinational logic node as a result. The voltage glitch then propagates through many combinational logic gates to a latch, which may cause the stored data within the latch to be corrupted if the glitch propagates to the input of the latch at the edge of a clock signal. This problem becomes more prevalent as the critical dimensions of transistors become smaller and smaller.
Known SEE hardening techniques for complementary-metal-oxide semiconductor (CMOS) processing technology include the usage of redundancy on combinational logic circuits and the usage of cross-coupled resistors or capacitors on storage cells. Redundancy typically includes at least two separate and independent circuits and a voting scheme to reduce the effect of SEEs. Added cross-coupled resistors and capacitors in a storage cell can slow down the ability of the storage cell to latch false data. However, each of the above-mentioned techniques has its drawbacks. For example, a typical voting scheme uses digital logic to recombine the redundant paths, and thereby actually provides amplification of SEEs. Also, the added cross-coupled resistors and capacitors in a storage cell introduce a more complicated fabrication process and results in a slower response to all input signals, thereby decreasing the operating speed of the storage cell. Consequently, it would be desirable to provide a better SEE hardening technique for removing glitches in digital logic circuits.
In accordance with a preferred embodiment of the present invention, a circuit for filtering single event effect (SEE) induced glitches comprises an SEE immune latch circuit and a delay element. The SEE immune latch circuit includes a first input, a second input, and an output. The SEE immune latch changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. The first input of the SEE immune latch circuit is directly connected to a signal input, and the second input of the SEE immune latch circuit is connected to the signal input via the delay element. The delay element provides a signal delay time equal to or greater than a pulse width of an SEE induced glitch but less than a pre-determined pulse width of an incoming signal at the signal input under normal operation. By connecting the delay element between the signal input and the second input of the SEE immune latch circuit, a temporal separation greater that the duration of an SEE induced glitch can be achieved on the data being drive into the first and the second inputs of the SEE immune latch circuit. As a result, SEE induced glitches will not be written into the SEE immune latch circuit.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.